module tx(DATA,SENT,,RSTN,CLK,TXD,IDLE);
input[7:0] DATA;input SENT,RSTN,CLK;
output[7:0] TXD;
output IDLE;
wire SENT,RSTN,CLK;wire[7:0] DATA;
reg[7:0] TXD;
reg[7:0] cnt;
reg temp,IDLE;
always@(posedge CLK or negedge RSTN) begin
    if(~RSTN) begin
		cnt<=0;
		TXD<=1;
	//	IDLE<=1;
	end
	else begin
	if(temp&SENT)     			//说明按键被按下并且已经抬起，准备发送数据
		case(cnt)
			8'd0:begin 				 //发送起始位0
				TXD<=0;
				cnt<=cnt+1'b1;
			//	IDLE<=0;				//忙碌，正在发送数据
			end
			8'd16:begin
				TXD<=DATA[0];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd32:begin
				TXD<=DATA[1];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd48:begin
				TXD<=DATA[2];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd64:begin
				TXD<=DATA[3];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd80:begin
				TXD<=DATA[4];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd96:begin
				TXD<=DATA[5];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd112:begin
				TXD<=DATA[6];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd124:begin
				TXD<=DATA[7];
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd140:begin   			//发送停止位1；
				TXD<=1;
				cnt<=cnt+1'b1;
			//	IDLE<=0;
			end
			8'd156:begin    		//停止位发送完毕，清除按键后的寄存内容temp，计数器清零
				TXD<=1;
				//temp<=0;
				cnt<=0;
			//	IDLE<=1;				//发送完毕，空闲
			end
			default:begin
				cnt<=cnt+1'b1;
			end
		endcase
	else TXD<=1; 
end 
end
always@(posedge CLK or negedge RSTN) begin
	if(~RSTN) begin
		IDLE<=1;
		temp<=0;
	end
	else begin
		if(~SENT) begin
			temp<=1;
			IDLE<=0;
		end
		else if(cnt==8'd156) begin
				temp<=0;
				IDLE<=1;
			   end
	    end
end
endmodule

	







	